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Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits
Supply Noise Power Gating Clock Gating Wavelet Analysis Linear Programming Genetic Algorithm
2014/12/8
In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks tha...