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Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs
Interface Trap Density Metrology state-of-the-art undoped Si n-FinFETs
2010/11/22
The presence of interface states at the MOS interface is a well-known cause of device gradation.This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can stron...